![]() ![]() Parametric cost modeling is done by statistically analyzing a large number of actual results and creating a model that matches as closely as possible. The second case is a large 28-layer circuit board similar to those found in servers.Īctivity-based cost modeling (ABC) and parametric cost modeling are the two dominant cost modeling methods. The first case is a small 10-layer board similar to most smartphone motherboards. Two example designs were chosen to analyze the cost of using this technology versus conventional interconnect. Here, the costs associated with manufacturing ELIC structures employing a Z-interconnect paste technology are outlined. These assembly advantages, coupled with proper design, offer cost advantages when products are built in large-scale production or in low-volume, high-mix assembly lines. Ability to join different materials in optimum press cycles.Separation of low- and high-speed signal channels.Improved performance through shorter traces.Making HDI layers using state-of-the-art conventional practices and then joining them to the core with paste-filled interconnect bonding layers provides design freedom to the client, excellent electrical properties for the device and higher yields with a reduced number of lamination cycles to the fabricator.Įvery layer interconnection (ELIC) and subassembly core-to-core interconnects are delivering: This manufacturing strategy produces more products in less time within the same manufacturing space. By breaking the outerlayers into subassemblies and using paste-filled interconnect bonding layers to join them to the core construction, the number of lamination cycles can be reduced and yields substantially improved. As designs approach the need to have five or more outer buildup layers containing stacked copper-plated microvias, fabricators seek relief from the repetitive lamination steps to save time, energy and water resources and to maintain yield. High-density-interconnect with anywhere, any-layer interconnects is the core technology that enables the miniaturization required for the feature-packed smartphone market segment. For another example, it would also permit the high-density portion of a circuit to be miniaturized, manufactured as an independent subassembly and then joined to the main portion of the circuit board so that the whole fits within the tight physical limits desired for a specific product. ![]() ![]() This same type of construction scheme can also enable the combination of multiple signal speed channels into a single construction. If a Z-interconnect scheme is employed, the rigid and flex subassemblies can be manufactured separately under their respective best-mode manufacturing techniques and then joined with a bonding layer containing paste-filled interconnects at high-Tg FR-4 temperatures (~180✬). Due to the imbalance in the mechanical characteristics (such as coefficient of thermal expansion) of base materials with conventional methods, these products are complex and cumbersome. The demand for rigid-flex products is increasing. This has the potential to significantly reduce time-to-market and manufacturing cost, and can enable assembly by breaking these complex structures into simpler mode-specific subunits that can be electrically interconnected at the end with paste-filled vias. This permits each mode-specific core or subassembly to be manufactured cost-effectively to best practices for that particular mode, and then joined into an integrated whole. Paste-filled interconnects permit the joining of mode-specific cores (e.g., flex) or subassemblies in single or multiple laminations. The industry is struggling with the complexity of mixed-mode, multiple-process-step manufacturing and cost-down targets. Used independently, both copper-plated and paste-filled interconnects have advantages for specific types of product structures, but when combined, the resulting design and manufacturing flexibility provide a path to bridge the divide between the IC and motherboard packaging requirements.Īpplications for high-layer count, complex RF design, high-density-interconnect and rigid-flex combinations are already manufactured in high volume, but the continuous demand is for smaller, lighter, thinner and lower-power-consumption products. Printed circuit board design and construction is meeting integrated circuit packaging requirements through any-layer interconnection schemes using combinations of copper-plated-microvias and paste-filled interconnects in stacked and offset configurations. Conductive paste instead of microvias can lower drilling costs and scrap rates. ![]()
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